HP-DMA Controller
Performance-IP's Direct Memory Access (DMA) Controller is designed to provide the highest performance transfers while keeping silicon and power to a minimum.
This controller incorporates just-in-time delivery of transfer data and prefetching of link-list descriptors. Both of these features reduce DMA buffering requirements to keep silicon area and power to a minimum. Providing the best performance/watt solution.
The HP-DMA Controller is designed to provide the highest performance AXI memory transfers. This controller incorporates up to eight independent configurable DMA channels, allowing multiple DMA transactions to be in-flight at anytime. The HP-DMA Controller has a configurable integrated RAM buffer, which is designed to provide just-in-time delivery of source to destination data transfers. This just-in-time operation allows more outstanding transactions to be in flight than traditional implementations. This improves performance of the HP-DMA Controller by reducing the impact of any high-latency devices.
The HP-DMA Controller also supports link-list DMA operation. This allows a host processor to define multiple DMA transfers by building a link-list in memory. The HP-DMA Controller will then transverse this link-list performing each DMA transfer. Only when all the transfers are complete will the DMA Controller interrupt the host processor, reducing processor involvement.
- Supports up to 8 independent DMA Channels
- Supports AXI3 and AXI4 bus protocols
- Configurable AXI Bus Widths of 32b, 64b, or 128b supported
- Supports memory to memory, memory to peripheral, peripheral to memory, and peripheral to peripheral transfers
- Link-list DMA operation
- Host processor interrupt support
- Watch Dog Timer Channel support
- Customer configurable integrated RAM buffer
